The present invention relates to a semiconductor memory device having a ferroelectric memory for storing data as a polarization value, to a method for fabricating the same, and to a method for driving the same.
Referring to FIGS. 22 to 25 and FIGS. 26A and 26B, a conventional semiconductor memory device will be described herein below.
FIG. 22 shows a memory cell and a peripheral circuit thereof in a conventional semiconductor memory device.
As shown in FIG. 22, the memory cell is a so-called 2T2C memory cell having two ferroelectric capacitors C0 and C1 and two pass transistors Q0 and Q1. The ferroelectric capacitor C0 has a first electrode connected to the source of the pass transistor Q0, while the ferroelectric capacitor C1 has a first electrode connected to the source of the pass transistor Q1. The ferroelectric capacitors C0 and C1 have respective second electrodes connected commonly to a cell plate line CP. The pass transistor Q0 has a drain connected to a bit line BL0, while the pass transistor Q1 has a drain connected to a bit line BL1. The bit line capacitance of the bit line BL0 is denoted by CBL0, while the bit line capacitance of the bit line BL1 is denoted by CBL1. The bit line capacitances CBL0 and CBL1 are equal to each other. The pass transistors Q0 and Q1 have respective gates connected commonly to a word line WL. A sense amplifier composed of inverters INV0 and INV1 is connected between respective one ends of the bit lines BL0 and BL1.
Each of the ferroelectric capacitors C0 and C1 retains polarization even in the state in which a voltage is not applied between the first and second electrodes and has a hysteresis loop 50 as shown in FIG. 23 in which, in the case where a positive voltage is applied to the plate line CP, the direction in which the voltage axis extends from left to right is designated as a positive direction and the direction in which the polarization axis extends upward is designated as a positive direction.
Data Write Operation
When data is written in the memory cell, a HIGH voltage is applied to the word line WL to turn ON the pass transistors Q0 and Q1 and then a pulse voltage of a positive polarity is applied to the plate line PL, while the bit lines BL0 and BL1 are placed at a LOW potential. As a result, the polarization value at the point 51 in FIG. 23 is written in each of the two ferroelectric capacitors C0 and C1.
If data “0” is written subsequently, a pulse voltage of the positive polarity is applied to the bit line BL1. As a result, the polarization state in the ferroelectric capacitor C1 follows the locus of the hysteresis loop 50 to reach the point 52 so that the polarization value at the point 52 is written in the ferroelectric capacitor C1.
If data “1” is written, on the other hand, a pulse voltage of the positive polarity is applied to the bit line BL0. As a result, the polarization state in the ferroelectric capacitor C0 follows the locus of the hysteresis loop 50 to reach the point 52 so that the polarization value at the point 52 is written in the ferroelectric capacitor C0. After the application of the write pulse voltage, the word line WL is placed at the LOW potential.
By the write operation, a positive polarization value (at the point 51) is stored in the ferroelectric capacitor C0 and a negative polarization value (at the point 52) is stored in the ferroelectric capacitor C1 if the data “0” is written. If the data “1” is written, on the other hand, the negative polarization value (at the point 52) is stored in the ferroelectric capacitor C0 and the positive polarization value (at the point 51) is stored in the ferroelectric capacitor C1. Thus, polarization values are written complementarily in the two ferroelectric capacitors C0 and C1.
Data Read Operation
When data is read from the memory cell, the bit lines BL0 and BL1 are precharged to the LOW potential, a HIGH voltage is applied to the word line WL to turn ON the pass transistors Q0 and Q1, and then a HIGH voltage is applied to the plate line CP. As a result, the ferroelectric capacitor in the polarization state at the point 51 follows the locus 53 shown in FIG. 24 to reach the polarization state at the point 54. On the other hand, the ferroelectric capacitor in the polarization state at the point 52 follows the locus 55 shown in FIG. 25 to reach the point 56.
Respective charges corresponding to the differences between the initial polarization states 51 and 52 and the new polarization states 54 and 56 are generated in the bit line capacitances CBL0 and CBL1 of the bit lines BL0 and BL1. The charges are converted to voltages with the bit line capacitances CBL0 and CBL1 and the resulting bit line potentials are amplified by the sense amplifier composed of the cross-coupled inverters INV0 and INV1 to be outputted. That is, if the polarization states at the points 51 and 52 are stored in the ferroelectric capacitors C0 and C1, the charge generated in the bit line BL0 (corresponding to the value difference between the points 54 and 51) is smaller than the charge generated in the bit line BL1 (corresponding to the value difference between the points 56 and 52) so that the bit line BL0 outputs the LOW potential. If the polarization states at the points 52 and 51 are stored in the ferroelectric capacitors C0 and C1, on the other hand, the charge generated in the bit line BL0 (corresponding to the value difference between the points 56 and 52) is larger than the charge generated in the bit line BL1 (corresponding to the value difference between the points 54 and 51) so that the bit line BL0 outputs a HIGH potential.
The output at the LOW potential from the bit line BL0 is determined as the data “0” since the polarization state stored in the former case corresponds to data “0” and the output at the HIGH potential from the bit line BL0 is determined as the data “1” since the polarization state stored in the latter case corresponds to data “1”, whereby the reading of data is performed correctly.
After the reading of data, the plate line CP is restored to the LOW potential. At this time, the polarization state in each of the two ferroelectric capacitors C0 and C1 follows the locus 57 shown in FIG. 24 or the locus 55 shown in FIG. 25 to reach the point 51 or 59.
Although the polarization values are stored complementarily prior to the initiation of the read operation, the polarization states of the same polarity are observed as a result of the read operation, which is a destructive read-out operation.
By performing the foregoing write operation again, the ferroelectric capacitors C0 and C1 are restored to the complementary polarization states prior to the initiation of the read operation, whereby the read operation is completed.
If the memory cell is left in a high-temperature environment with the polarization states being stored in the ferroelectric capacitors composing the memory cell, the problem is encountered that the polarization states are printed and polarization inversion is hard to occur. This is termed imprinting and, in an imprinted ferroelectric capacitor, the hysteresis characteristic shifts in the direction of the voltage axis so that the amount of charge generated during the data read operation is reduced and the problem of reduced operating margin occurs. The problem will be described herein below in detail.
As described above, the two ferroelectric capacitors C0 and C1 complementarily store polarization values in the conventional semiconductor memory device. FIG. 26A shows the case where a positive polarization value (at the point 51) is stored. FIG. 26B shows the case where a negative polarization value (at the point 52) is stored. In the initial state, each of the two ferroelectric capacitors C0 and C1 has the hysteresis loop 60 indicated by the broken curve and they have coincident characteristics. If the ferroelectric capacitors C0 and C1 are left in a high-temperature environment (e.g., 85° C.) for a long period of time (e.g., 100 hours), the hysteresis loop 60 shifts in the direction of the voltage axis. The direction of shifting is dependent on the polarization stored. In the case shown in FIG. 26A, the positive polarization value (at the point 51) is stored so that the hysteresis loop 60 shifts in the direction of negative voltage to provide a hysteresis loop 61. In the case shown in FIG. 26B, the negative polarization value (at the point 52) is stored so that the hysteresis loop 60 shifts in the direction of positive voltage to provide a hysteresis loop 62.
Even if the semiconductor memory device is restored to a normal operating temperature (e.g., 27° C.), the ferroelectric capacitors in each of which the hysteresis loop has shifted are no more restored to the initial hysteresis loop 60 so that the hysteresis loops 61 and 62 resulting from shifting are retained.
The locus followed when a data read operation is performed has changed from the initial state. The charge generated in the case of FIG. 26A corresponds to the value difference between the points 63 and 51, while the charge generated in the case of FIG. 26B corresponds to the value difference between the points 64 and 52. It will be understood that, in the case of FIG. 26B where a negative polarization value is stored, the amount of generated charge becomes smaller than in the initial state indicated by the broken curve. This decreases the potential difference between the bit lines BL0 and BL1 and reduces operating margin for the amplification by the sense amplifier composed of the cross-coupled inverters INV0 and INV1 and the output thereof.
In the imprinted ferroelectric capacitor, a problem is also encountered during a data rewrite operation. That is, if the polarization value (at the point 51) in FIG. 26A and the polarization value (at the point 52) in FIG. 26B are rewritten to have opposite polarities, the value at the point 65 in FIG. 26A and the value at the point 66 in FIG. 26B are written as the polarization values. Thus, the difference between the polarization values (corresponding to the value difference between the points 66 and 65) in the two ferroelectric capacitors C0 and C1 is smaller than the difference between the polarization values (corresponding to the value difference between the points 51 and 52) so that data retention property is degraded.